/*
 * Copyright : (C) 2023 Termony Technology, Inc. All Rights Reserved.
 */

#ifndef RK3588_PARAMTERERS_H
#define RK3588_PARAMTERERS_H

#ifdef __cplusplus
extern "C"
{
#endif

/* CORE */
#define CORE0_AFF   0x0
#define CORE1_AFF   0x1
#define CORE2_AFF   0x2
#define CORE3_AFF   0x3
#define RKCORE_NUM  4

/* CACHE */
#define CACHE_LINE_ADDR_MASK 0x3FUL
#define CACHE_LINE  64U

/* Memory address mapping region */
#define RK_MEMORY_MAP_ADDR 0x20000000UL
#define RK_MEMORY_MAP_SIZE 0x10000000UL /* 256MB */

/* Device address mapping region */
#define RK_DEVICE_MAP_ADDR 0xF0000000UL
#define RK_DEVICE_MAP_SIZE 0x10000000UL /* 256MB */

/* PCIe address mapping region */
#define RK_PCIE_MAP_ADDR 0x300000000ULL
#define RK_PCIE_MAP_SIZE 0x100000000ULL /* 4GB */

/* GIC */
#define GIC_VERSION     3
#define GIC_BASE_ADDR   0xFD400000U
#define GICD_BASE_ADDR  (GIC_BASE_ADDR + 0)
#define GITS_BASE_ADDR  (GIC_BASE_ADDR + 0x40000U)
#define GICR_BASE_ADDR  (GIC_BASE_ADDR + 0x60000U)

/* SGRF */
#define SYS_SGRF_BASE_ADDR      0xFDD18000U

/* GRF */
#define PMU_GRF_BASE_ADDR       0xFDC20000U
#define CPU_GRF_BASE_ADDR       0xFDC30000U
#define DDR_GRF_BASE_ADDR       0xFDC40000U
#define PIPE_GRF_BASE_ADDR      0xFDC50000U
#define SYS_GRF_BASE_ADDR       0xFDC60000U
#define PIPE_PHY0_GRF_BASE_ADDR 0xFDC70000U
#define PIPE_PHY1_GRF_BASE_ADDR 0xFDC80000U
#define PIPE_PHY2_GRF_BASE_ADDR 0xFDC90000U
#define USBPHY_U2_GRF_BASE_ADDR 0xFDCA0000U
#define USBPHY_U3_GRF_BASE_ADDR 0xFDCA8000U
#define EDP_PHY_GRF_BASE_ADDR   0xFDCB0000U
#define PCIE3_PHY_GRF_BASE_ADDR 0xFDCB8000U
#define USB_GRF_BASE_ADDR       0xFDCF0000U

/* GPIO */
#if !defined(__ASSEMBLER__)
enum {
    GPIO0_ID = 0,
    GPIO1_ID,
    GPIO2_ID,
    GPIO3_ID,
    GPIO4_ID,
    GPIO_NUM
};
#endif

#define GPIO0_IRQ_NUM 65
#define GPIO1_IRQ_NUM 66
#define GPIO2_IRQ_NUM 67
#define GPIO3_IRQ_NUM 68
#define GPIO4_IRQ_NUM 69

#define GPIO_REG_LENGTH 0x10000U

#define GPIO0_BASE_ADDR 0xFDD60000U
#define GPIO1_BASE_ADDR 0xFE740000U
#define GPIO2_BASE_ADDR 0xFE750000U
#define GPIO3_BASE_ADDR 0xFE760000U
#define GPIO4_BASE_ADDR 0xFE770000U

/* PWM */
#if !defined(__ASSEMBLER__)
enum {
    PWM0_ID = 0,
    PWM1_ID,
    PWM2_ID,
    PWM3_ID,
    PWM_NUM
};
#endif

#define PWM0_IRQ_NUM 114
#define PWM1_IRQ_NUM 115
#define PWM2_IRQ_NUM 116
#define PWM3_IRQ_NUM 117
#define PWM0_PWR_IRQ_NUM 118
#define PWM1_PWR_IRQ_NUM 119
#define PWM2_PWR_IRQ_NUM 120
#define PWM3_PWR_IRQ_NUM 121

#define PWM_REG_LENGTH 0x10000U

#define PWM0_BASE_ADDR 0xFDD70000U
#define PWM1_BASE_ADDR 0xFE6E0000U
#define PWM2_BASE_ADDR 0xFE6F0000U
#define PWM3_BASE_ADDR 0xFE700000U

/* DMAC */
#if !defined(__ASSEMBLER__)
enum {
    DMAC0_ID = 0,
    DMAC1_ID,
    DMAC_NUM
};
#endif

#define DMAC0_IRQ_NUM 46
#define DMAC0_ABORT_IRQ_NUM 45
#define DMAC1_IRQ_NUM 48
#define DMAC1_ABORT_IRQ_NUM 47

#define DMAC0_NS_BASE_ADDR 0xFE530000U
#define DMAC1_NS_BASE_ADDR 0xFE550000U

#define DMAC0_S_BASE_ADDR  0xFE510000U
#define DMAC1_S_BASE_ADDR  0xFE540000U

#define DMAC_REG_LENGTH    0x10000U /* 64KB */

/* I2C */
#if !defined(__ASSEMBLER__)
enum {
    I2C0_ID = 0,
    I2C1_ID,
    I2C2_ID,
    I2C3_ID,
    I2C4_ID,
    I2C5_ID,
    I2C_NUM
};
#endif

#define I2C0_IRQ_NUM 78
#define I2C1_IRQ_NUM 79
#define I2C2_IRQ_NUM 80
#define I2C3_IRQ_NUM 81
#define I2C4_IRQ_NUM 82
#define I2C5_IRQ_NUM 83

#define I2C_REG_LENGTH 0x10000U

#define I2C0_BASE_ADDR 0xFDD40000U
#define I2C1_BASE_ADDR 0xFE5A0000U
#define I2C2_BASE_ADDR 0xFE5B0000U
#define I2C3_BASE_ADDR 0xFE5C0000U
#define I2C4_BASE_ADDR 0xFE5D0000U
#define I2C5_BASE_ADDR 0xFE5E0000U

/* SPI */
#if !defined(__ASSEMBLER__)
enum {
    SPI0_ID = 0,
    SPI1_ID,
    SPI2_ID,
    SPI3_ID,
    SPI4_ID,
    SPI_NUM
};
#endif

#define SPI0_IRQ_NUM 135
#define SPI1_IRQ_NUM 136
#define SPI2_IRQ_NUM 137
#define SPI3_IRQ_NUM 138

#define SPI_REG_LENGTH 0x10000U

#define SPI0_BASE_ADDR 0xFE610000U
#define SPI1_BASE_ADDR 0xFE620000U
#define SPI2_BASE_ADDR 0xFE630000U
#define SPI3_BASE_ADDR 0xFE640000U

/* UART */
#if !defined(__ASSEMBLER__)
enum {
    UART0_ID = 0,
    UART1_ID,
    UART2_ID,
    UART3_ID,
    UART4_ID,
    UART5_ID,
    UART6_ID,
    UART7_ID,
    UART8_ID,
    UART9_ID,
    UART_NUM
};
#endif

#define UART0_IRQ_NUM 148
#define UART1_IRQ_NUM 149
#define UART2_IRQ_NUM 150
#define UART3_IRQ_NUM 151
#define UART4_IRQ_NUM 152
#define UART5_IRQ_NUM 153
#define UART6_IRQ_NUM 154
#define UART7_IRQ_NUM 155
#define UART8_IRQ_NUM 156
#define UART9_IRQ_NUM 157

#define UART_REG_LENGTH 0x10000U

#define UART0_BASE_ADDR 0xFDD50000U
#define UART1_BASE_ADDR 0xFE650000U
#define UART2_BASE_ADDR 0xFE660000U
#define UART3_BASE_ADDR 0xFE670000U
#define UART4_BASE_ADDR 0xFE680000U
#define UART5_BASE_ADDR 0xFE690000U
#define UART6_BASE_ADDR 0xFE6A0000U
#define UART7_BASE_ADDR 0xFE6B0000U
#define UART8_BASE_ADDR 0xFE6C0000U
#define UART9_BASE_ADDR 0xFE6D0000U

/* GMAC */
#if !defined(__ASSEMBLER__)
enum {
    GMAC0_ID = 0,
    GMAC1_ID = 0,
    GMAC_NUM
};
#endif

#define GMAC0_LPI_IRQ_NUM 55
#define GMAC0_PMT_IRQ_NUM 56
#define GMAC0_SBD_IRQ_NUM 59
#define GMAC0_SBD_PERCH_RX0_IRQ_NUM 57
#define GMAC0_SBD_PERCH_TX0_IRQ_NUM 58

#define GMAC1_LPI_IRQ_NUM 60
#define GMAC1_PMT_IRQ_NUM 61
#define GMAC1_SBD_IRQ_NUM 64
#define GMAC1_SBD_PERCH_RX0_IRQ_NUM 62
#define GMAC1_SBD_PERCH_TX0_IRQ_NUM 63

#define GMAC_REG_LENGTH 0x10000U

#define GMAC0_BASE_ADDR 0xFE2A0000U
#define GMAC1_BASE_ADDR 0xFE010000U

/* CAN */
#if !defined(__ASSEMBLER__)
enum {
    CAN0_ID = 0,
    CAN1_ID = 0,
    CAN2_ID = 0,
    CAN_NUM
};
#endif

#define CAN0_DMA_IRQ_NUM 33
#define CAN1_DMA_IRQ_NUM 34
#define CAN2_DMA_IRQ_NUM 35

#define CAN0_BASE_ADDR 0xFE570000U
#define CAN1_BASE_ADDR 0xFE580000U
#define CAN2_BASE_ADDR 0xFE590000U
#define CAN_REG_LENGTH 0x10000U /* 64KB */

/* FSPI */
#if !defined(__ASSEMBLER__)
enum {
    FSPI0_ID = 0,
    FSPI_NUM
};
#endif

#define FSPI_IRQ_NUM   133

#define FSPI_BASE_ADDR  0xFE300000U
#define FSPI_REG_LENGTH 0x10000U /* 64KB */

/* EMMC */
#if !defined(__ASSEMBLER__)
enum {
    EMMC0_ID = 0,
    EMMC_NUM
};
#endif

#define EMMC_IRQ_NUM   51

#define EMMC_BASE_ADDR  0xFE310000U
#define EMMC_REG_LENGTH 0x10000U /* 64KB */

/* SDMMC */
#if !defined(__ASSEMBLER__)
enum {
    SDMMC0_ID = 0,
    SDMMC1_ID,
    SDMMC2_ID,
    SDMMC_NUM
};
#endif

#define SDMMC0_IRQ_NUM 130
#define SDMMC1_IRQ_NUM 131
#define SDMMC2_IRQ_NUM 132

#define SDMMC0_BASE_ADDR    0xFE2B0000U
#define SDMMC1_BASE_ADDR    0xFE2C0000U
#define SDMMC2_BASE_ADDR    0xFE000000U
#define SDMMC_BUF_BASE_ADDR 0xFE480000U
#define SDMMC_REG_LENGTH    0x10000U /* 64KB */

/* NANDDC */
#if !defined(__ASSEMBLER__)
enum {
    NANDDC0_ID = 0,
    NANDDC_NUM
};
#endif

#define NANDDC0_IRQ_NUM 102

#define NANDDC_BASE_ADDR  0xFE330000U
#define NANDDC_REG_LENGTH 0x10000U /* 64KB */

/* SATA */
#if !defined(__ASSEMBLER__)
enum {
    SATA0_ID = 0,
    SATA1_ID,
    SATA2_ID,
    SATA_NUM
};
#endif

#define SATA0_IRQ_NUM 126
#define SATA1_IRQ_NUM 127
#define SATA2_IRQ_NUM 128

#define SATA0_BASE_ADDR 0xFC000000U
#define SATA1_BASE_ADDR 0xFC400000U
#define SATA2_BASE_ADDR 0xFC800000U
#define SATA_REG_LENGTH 0x400000U /* 4MB */

/* WDT */
#if !defined(__ASSEMBLER__)
enum {
    WDT0_ID = 0,
    WDT_NUM
};
#endif


#define WDT0_NS_IRQ_NUM 182
#define WDT0_S_IRQ_NUM  181

#define WDT0_NS_BASE_ADDR 0xFE600000U
#define WDT0_S_BASE_ADDR  0xFE3C0000U
#define WDT_REG_LENGTH  0x10000U /* 64KB */

/* TIMER_S */
#if !defined(__ASSEMBLER__)
enum {
    TIMER0_S_ID = 0,
    TIMER1_S_ID,
    TIMER_S_NUM
};
#endif

#define TIMER0_S_IRQ_NUM 139
#define TIMER1_S_IRQ_NUM 140

#define TIMER_S_REG_LENGTH 0x4000U

#define TIMER_S_BASE_ADDR  0xFDD1C000U

/* TIMER */
#if !defined(__ASSEMBLER__)
enum {
    TIMER0_ID = 0,
    TIMER1_ID,
    TIMER2_ID,
    TIMER3_ID,
    TIMER4_ID,
    TIMER5_ID,
    TIMER_NUM
};
#endif

#define TIMER0_IRQ_NUM 141
#define TIMER1_IRQ_NUM 142
#define TIMER2_IRQ_NUM 143
#define TIMER3_IRQ_NUM 144
#define TIMER4_IRQ_NUM 145
#define TIMER5_IRQ_NUM 146

#define TIMER_NS_REG_LENGTH 0x10000U

#define TIMER_NS_BASE_ADDR 0xFE5F0000U

/* USB */
#if !defined(__ASSEMBLER__)
enum {
    USB3OTG0_ID = 0,
    USB3OTG1_ID,
    USB2HOST0_ID,
    USB2HOST1_ID,
    USB_NUM
};
#endif

#define USB3OTG_0_IRQ_NUM 201
#define USB3OTG_1_IRQ_NUM 202
#define USB2HOST_0_ARB_IRQ_NUM  161
#define USB2HOST_0_EHCI_IRQ_NUM 162
#define USB2HOST_0_OHCI_IRQ_NUM 163
#define USB2HOST_1_ARB_IRQ_NUM  164
#define USB2HOST_1_EHCI_IRQ_NUM 165
#define USB2HOST_1_OHCI_IRQ_NUM 166

#define USB3OTG_0_BASE_ADDR      0xFCC00000U
#define USB3OTG_1_BASE_ADDR      0xFD000000U
#define USB2HOST_0_BASE_ADDR     0xFD800000U
#define USB2HOST_1_BASE_ADDR     0xFD880000U
#define USB2PHY_U3OTG_BASE_ADDR  0xFE8A0000U
#define USB2PHY_U2HOST_BASE_ADDR 0xFE8B0000U

/* CSI */
#if !defined(__ASSEMBLER__)
enum {
    CSI0_ID = 0,
    CSI_NUM
};
#endif

#define CSI_RX_CTRL0_BASE_ADDR 0xFDFA0000U
#define CSI_RX_CTRL1_BASE_ADDR 0xFDFB0000U
#define CSI_RX_PHY_BASE_ADDR   0xFE870000U
#define CSI_REG_LENGTH 0x10000U /* 64KB */

/* DSI */
#if !defined(__ASSEMBLER__)
enum {
    DSI0_ID = 0,
    DSI_NUM
};
#endif

#define DSI_TX0_BASE_ADDR     0xFE060000U
#define DSI_TX1_BASE_ADDR     0xFE070000U
#define DSI_TX_PHY0_BASE_ADDR 0xFE850000U
#define DSI_TX_PHY1_BASE_ADDR 0xFE860000U
#define DSI_REG_LENGTH        0x10000U /* 64KB */

/* eDP */
#define EDP0_BASE_ADDR      0xFE0C0000U
#define EDP_REG_LENGTH      0x10000U /* 64KB */

/* HDMI */
#if !defined(__ASSEMBLER__)
enum {
    HDMI0_ID = 0,
    HDMI_NUM
};
#endif

#define HDMI0_WAKEUP_IRQ_NUM 76
#define HDMI0_IRQ_NUM 77

#define HDMI0_BASE_ADDR 0xFE0A0000U
#define HDMI_REG_LENGTH 0x20000U /* 128KB */

/* I2S */
#if !defined(__ASSEMBLER__)
enum {
    I2S0_ID = 0,
    I2S1_ID,
    I2S2_ID,
    I2S3_ID,
    I2S_NUM
};
#endif

#define I2S0_8CH_IRQ_NUM 84
#define I2S1_8CH_IRQ_NUM 85
#define I2S2_2CH_IRQ_NUM 86
#define I2S3_2CH_IRQ_NUM 87

#define I2S0_8CH_BASE_ADDR 0xFE400000U
#define I2S1_8CH_BASE_ADDR 0xFE410000U
#define I2S2_2CH_BASE_ADDR 0xFE420000U
#define I2S3_2CH_BASE_ADDR 0xFE430000U
#define I2S_REG_LENGTH     0x10000U /* 64KB */

/* PDM */
#if !defined(__ASSEMBLER__)
enum {
    PDM0_ID = 0,
    PDM_NUM
};
#endif

#define PDM0_BASE_ADDR 0xFE440000U
#define PDM_REG_LENGTH 0x10000U /* 64KB */

/* SPDIF */
#if !defined(__ASSEMBLER__)
enum {
    SPDIF0_ID = 0,
    SPDIF_NUM
};
#endif

#define SPDIF_8CH_BASE_ADDR 0xFE460000U
#define SPDIF_REG_LENGTH    0x10000U /* 64KB */

/* CRYPTO */
#if !defined(__ASSEMBLER__)
enum {
    CRYPTO0_ID = 0,
    CRYPTO_NUM
};
#endif

#define CRYPTO_NS_IRQ_NUM 36

#define CRYPTO_NS_BASE_ADDR  0xFE380000U

/* TRNG */
#if !defined(__ASSEMBLER__)
enum {
    TRNG0_ID = 0,
    TRNG_NUM
};
#endif

#define TRNG_NS_BASE_ADDR   0xFE388000U
#define TRNG_S_BASE_ADDR    0xFE370000U

/* SPINLOCK */
#if !defined(__ASSEMBLER__)
enum {
    SPINLICK0_ID = 0,
    SPINLICK_NUM
};
#endif

#define SPINLOCK_BASE_ADDR  0xFDE30000U

/* MAILBOX( for MCU) */
#if !defined(__ASSEMBLER__)
enum {
    MAILBOX0_ID = 0,
    MAILBOX_NUM
};
#endif

#define MAILBOX0_CA55_0_IRQ_NUM 215
#define MAILBOX0_CA55_1_IRQ_NUM 216
#define MAILBOX0_CA55_2_IRQ_NUM 217
#define MAILBOX0_CA55_3_IRQ_NUM 218
#define MAILBOX0_MCU_0_IRQ_NUM  219
#define MAILBOX0_MCU_1_IRQ_NUM  220
#define MAILBOX0_MCU_2_IRQ_NUM  221
#define MAILBOX0_MCU_3_IRQ_NUM  222

#define MAILBOX0_BASE_ADDR 0xFE780000U

/* PCIE3 */
#if !defined(__ASSEMBLER__)
enum {
    PCIE3_X2_ID = 0,
    PCIE3_X1_ID,
    PCIE2_X1_ID,
    PCIE_NUM
};
#endif

#define PCIE3_X2_ERR_IRQ_NUM    193
#define PCIE3_X2_LEGACY_IRQ_NUM 194
#define PCIE3_X2_MSG_RX_IRQ_NUM 195
#define PCIE3_X2_PMC_IRQ_NUM    196
#define PCIE3_X2_SYS_IRQ_NUM    197
#define PCIE3_X1_ERR_IRQ_NUM    188
#define PCIE3_X1_LEGACY_IRQ_NUM 189
#define PCIE3_X1_MSG_RX_IRQ_NUM 190
#define PCIE3_X1_PMC_IRQ_NUM    191
#define PCIE3_X1_SYS_IRQ_NUM    192
#define PCIE2_X1_ERR_IRQ_NUM    103
#define PCIE2_X1_LEGACY_IRQ_NUM 104
#define PCIE2_X1_MSG_RX_IRQ_NUM 105
#define PCIE2_X1_PMC_IRQ_NUM    106
#define PCIE2_X1_SYS_IRQ_NUM    107

#define PCIE3_X2_S_BASE_ADDR    0xF0000000U
#define PCIE3_X1_S_BASE_ADDR    0xF2000000U
#define PCIE2_X1_S_BASE_ADDR    0xF4000000U
#define PCIE3_X2_DBI_BASE_ADDR  0xF6000000U
#define PCIE3_X1_DBI_BASE_ADDR  0xF6400000U
#define PCIE2_X1_DBI_BASE_ADDR  0xF6800000U
#define PCIE3_X2_APB_BASE_ADDR  0xFE280000U
#define PCIE3_X1_APB_BASE_ADDR  0xFE270000U
#define PCIE2_X1_APB_BASE_ADDR  0xFE260000U
#define PCIE3_PHY_BASE_ADDR     0xFE8C0000U

#define PCIE3_X2_S_ZONE_ADDR    0x300000000ULL
#define PCIE3_X1_S_ZONE_ADDR    0x340000000ULL
#define PCIE2_X1_S_ZONE_ADDR    0x380000000ULL
#define PCIE3_ZONE_LENGTH       0x40000000U /* 1GB */

#define PCIE3_X2_DBI_ZONE_ADDR  0x3C0000000ULL
#define PCIE3_X1_DBI_ZONE_ADDR  0x3C0400000ULL
#define PCIE1_X1_DBI_ZONE_ADDR  0x3C0800000ULL
#define PCIE3_DBI_ZONE_LENGTH   0x400000U /* 4MB */

#ifdef __cplusplus
}

#endif

#endif /* RK3588_PARAMTERERS_H */